![Design of positive & negative edge triggered D-flip flop using AlGaAs/GaAs MODFET technology | Semantic Scholar Design of positive & negative edge triggered D-flip flop using AlGaAs/GaAs MODFET technology | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/32dc1450e0849f114ed5845ef4ecb0eb8e0ace5d/2-Figure2-1.png)
Design of positive & negative edge triggered D-flip flop using AlGaAs/GaAs MODFET technology | Semantic Scholar
![This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was](https://i.redd.it/cv6hms38j8051.jpg)
This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was
![flipflop - How to implement a negative edge triggered D Flip Flop (Master Slave Configuration)? - Electrical Engineering Stack Exchange flipflop - How to implement a negative edge triggered D Flip Flop (Master Slave Configuration)? - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/zjvtg.png)